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# What is clock uncertainity and why does it happen?

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#### elec_student

##### Member level 1
Hi Guys,

Can anybody explain me clock uncertainity and its reason?

how much clock uncertainity

clock uncertainity is nothing but clock jitter and skew.

how to decide the clock uncertainity

Hi,

Then what is the difference between clock skew & clock uncertainty??

tranision time skew uncertainty

I believe clock skew and clock uncertainty refer to the same thing which refer to the different between 2 clock path.

But normally clock uncertainty is refer to the target skew during the synthesis before the designer get the actual skew after CTS.

Hope this help. Thanks.

clock skew analysis and post layout synthesis

I didnt get ur answer..pls explain it elaborately...

clock uncertainities

plz explain ur question in brief.

clock tree jitter analysis

Let me see if I remember this correctly. From a synthesis point of view, you apply clock uncertainity and clock skew the same way. But if you are trying to understand what they mean in a physical domain, clock uncertainity is some margin that you add to the clock edge because you are not sure at what time the event will occur. This can happen for various reasons and usually you apply clock uncertainity in design analisis when the clock tree synthesis (CTS) is not done. CTS essentially balences out the clock tree. Skew is a delay (+ve or negative) you see for a clock edge due to some delay cells or something like that.

Timing Gurus, please correct me if I am wrong.

Re: clock uncertainity

one other thing I can add here is that signal skew usually builds up as one traverses the logic along clock trees. This always increases as we move away from the clock source. It is a pre-layout number. It is a best guess estimate. It is a place holder for the actual post-layout delays and as such is used only for pre-layout analysis. Jitter, on the other hand, is a lumped-sum number representing all other uncertainties which are beyond our controls such as; PLL or crystal imperfections, cell and wire technology deviations and fluctuations across different PVT corners. Jitter applies to both pre and post layout analysis as the others already mentioned.

clock uncertainity

1) for pre-layout designs :
clock uncertainity = skew + jitter

2) for post-layout designs :
clock uncertainity = jitter

B4 CTS there is no way of knowing what is the delay in the clock tree. so an approximate value has to be used while performing the " pre-layout STA"

After CTS is performed ( propogatd clock mode), the delay values will be propogated along the clock path and hence skew will be eliminated !!

jitter : none of the PLLs are perfect, the small variations in the clock signal generated by the PLLs is known as "jitter" . jitter will normally be a fixed value !

WBR,
Lakshman

liuyaohua6

### liuyaohua6

Points: 2

Re: clock uncertainity

lakshman.ar said:
and hence skew will be eliminated !!

WBR,
Lakshman

The clock uncertainty exists in real world. The only difference between pre-layout and post-layout is that the clock uncertainty is estimated by engineer before layout, (because we need a estimated value for DC)and the clock uncertainty is real, not determined by engineer after layout.

Because after layout, all signal delay in chip are fixed.

David

clock uncertainity

uncertainity is unpredicatablity of signal arrival...this may be due to noise or different delays on path reaching a point ...

signal generator may hav sme uncertainiity

Re: clock uncertainity

The spatial variation in arrival time of a clock transition is commonly referred as a clock skew.
Clock jitter refers to the temporal variations of the clock period at a given point on the chip, that is the clock period can reduce or expand on a cycle by cycle basis.

Re: clock uncertainity

Sometimes clock skew is helpful to us . It decreaes the time period of the clock and increases the frequency, as i the case of positive skew .

Re: clock uncertainity

Can u Explain,How Skew can decrease the period??

Regards

Re: clock uncertainity

Asha_eda said:
Can u Explain,How Skew can decrease the period??

Regards

Hi Asha, you can refer "Digital Integrated Circuits" by Rabaey page no. 496
regards,
santhosh

clock uncertainity

clock skew is mainly delay in clock arrival between different points due to different clock network from clock source to those points.

clock uncertainty is variation in clock period for one point, regardless of other points.

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