What is attribute and allias in VHDL ?

[master_picengineer]

What is attribute and allias in VHDL.
Please provide an exemple.
Are these instructions recognized by synthesis tool like DC ?
Thanks

 

[avimit]

Re: Attribute and Allias

An attribute gives info about vhdl objects such as signals.
Some of them are synthesizeable such as 'left 'right 'length, while others are not such as 'delayed 'image.
Alias is another name given to a signal for 'readability'. I would think they will be ignored by synthesis tools.
Kr,
Avi
http://www.vlsiip.com[/img]

 

[master_picengineer]

Attribute and Allias

Thanks you Avimit.
Cheers,
Master_Pic_Engineer