Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is a via array and how is it used?

Status
Not open for further replies.

S.Nikhil

Member level 1
Joined
Oct 9, 2007
Messages
34
Helped
18
Reputation
36
Reaction score
17
Trophy points
1,288
Activity points
1,553
Hi,

What is an via array. Explain its usage during power routing and the impact on power routing.

How to decide the number of vias in an via array.

How is an via array represented in a LEF. Can we add custom via arrays to the LEF file.

Does the addition of via array reduce the resistance.

Thx

S.Nikhil
 

Re: vi a array

A via array (or 'via farm') is a group of vias arranged in a regular pattern of rows and columns, and that are all on the same net.

Via arrays are usually used when a wide wire changes layer (e.g.: power or ground wire). These wires are wide because they have to carry a lot of current. A single via is not able to carry sufficient current, so you need either (a) a much bigger via, or (b) more of the regular small vias connected in parallel (i.e.: placed next to each other). For manufacturability reasons the fabs prefer all vias to be the same size, so everybody uses solution (b).

In summary, when wide wires change layer they do so through multiple vias arranged in an array pattern. The size of the array is determined by the current carrying capacity of the vias and the amount of current you need to conduct. In practice, the via array is always made as big as possible to cover the entire overlap area between the wire segments on the 2 layers (the more the merrier).

The other reasons to do this are:
- to reduce the via resistance (yes, vias arranged in parallel reduce the net resistance for the layer transition)
- to avoid electro-migration issues, and
- to improve yield by providing via redundancy

Via arrays can be represented in LEF with the following command:

VIA ...
VIARULE ....
ROWCOL <= specify the number of rows and colums in the array

You can define your own VIARULE
 
  • Like
Reactions: zazar

    zazar

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top