Hot carrier effects have nothing to do with high speed. They are
all about the field vector sum in oxide-adjacent regions.
There's nothing much you can do about the vertical field in
an IC. Gate ox thickness and application supply voltage are
intimately coupled in process design / reliability rating.
To get a lateral field that does not make HCE the device
reliability limiter (rather than oxide wearout, the primary
or most fundamental limit) you have to spread the depletion
region at the D-B junction adjoining the spacer and gate. The
spacer is really the more serious problem as its oxide
quality is low and volume large.
An abrupt D-B junction as formed in the simplest CMOS
transistor, has a high field that is one-sided (all depletion
spreads into the body). This maximizes dL/dv, early punchthrough
or impact ionization (and such ionization is where those
"hot" carriers come from).
If you make a lightly doped drain region between gate and
contact, the depletion region can spread in both directions
and voltage is dropped across greater distance netting
a lower field. The DMOS device is the furthest "extension"
(heh) of this principle. LDD is more of a "cheap cheat".
generally not using additional masks but depending on the
spacer oxide as a hard mask with a high-tilt implant making
the LDD underlap of spacer so that Leff comes out near Ldrawn
and LDD region length is about the spacer extent (S/D
implant will step on it wherever a straight vertical shot through
the N+, P+
masks hit).
Often (or usually) LDD is also present at the source, making
an inferior drive, but improved linearity device (the source
is in effect resistor-degenerated). However I have seen
masked drain extensions in older, medium to high voltage
processes.
Now, why the urgency to our answers whan all of this info
is so commonly available?