what inputs we should have from designer before starting the layout of standard cells

[ms_90]

i am working in analog layouts but need to learn about the std cell development process. So can anybody please help me with this question?

 

[dick_freebird]

You would probably start off with things that are sort of
philosophical in nature. Such as, channel or channel-less
routing? What interconnect plane to route power/ground?
Contacts in the cell core, or stubbed out? That kind of thing.
These constrain the application / construction in Met1 and
maybe Met2, at the least. Then you want to figure out any
"special" rules (like, maybe a 2-contact-per-finger minimum,
a width maximum per finger for gate resistance and
electromigration, etc.). The tradeoff between rack height and
cell width depends somewhat on what you expect the cell
usage mix to be, short or tall will be wasteful in different
ways / mixes but an optimum exists for density at any mix
you care to assert.

Poly routing internal, allowed or not? Big difference to
final cell size when there is internal complexity (like FFs).
Racks flip-and-butt, sharing busses or spacing them
independent? Tradeoff there is some core rail integrity
vs density. And just what is the required bus width?
That depends on worst logic-glitch loading (and this
in turn, the worst-case driven loads) and the max die
dimension (assume busses are end-fed only, what is
the center-of-die rail span droop and individual rail
peak excursion from periphery bus as reference,
against noise margin requirements and the timing
skew padding built into the library?

 

[ms_90]

thanks dick_freebird