what happens when hold time (15nsec) greater than setup time (3nse)
then whether we can abale to calculate the clock frequency when propagation dealy is provided (say 4nsec) .............
my dout is what will happen whe hold time is far more than setup time
if u have any sequential circuits for calculating setup time clock freq and other timing things for interviews plz do forward me
The only relation between hold time and setup time is:
th(hold) + ts(setup) >= 0,
this is a very important concept, especially when you meet the negative value of hold time.