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what happens if hold time greater than setup time

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kil

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hi all
i have a question for all plz hgelp me

what happens when hold time (15nsec) greater than setup time (3nse)
then whether we can abale to calculate the clock frequency when propagation dealy is provided (say 4nsec) .............


my dout is what will happen whe hold time is far more than setup time


if u have any sequential circuits for calculating setup time clock freq and other timing things for interviews plz do forward me

or plz suggest some good sites for them

krushi
 

sameer_dlh25

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I think there is no relation between setup and hold time

for normal flop to flop path i.e.

FF1 --> Combinational logic with delay (td) --> FF2


if FF1/FF2 clock to q delay is tcq and set up and hold time are ts and th then basic equations are

tc > tcq + td + ts
th < tcq + td

This is the base of all flop base designs.
:idea:
 

dr.farnsworth

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How can i find value of ts ? is it setup time of lib element or FF's?


Regards,
Dr.farnsworth
 

kgeorge123

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Dude,

Setup and Hold times have not relations with each other.It is the property of the FFs in the libs. Check below
 

jarodz

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The only relation between hold time and setup time is:
th(hold) + ts(setup) >= 0,
this is a very important concept, especially when you meet the negative value of hold time.

Sincerely,
Jarod
 

yuenkit

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provided your clock period > hold time + setup time, there should be no problem.

if hold time = 3ns, setup time = 1ns (hold > setup time), and your clock period = 10ns

so, hold time means, ur signal should arrive aft 3 ns, setup time means your signal should arrive before (10 - 1) = 9 ns,

thus ur signal should arrive in x ns, where 3 < x < 9.
 
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