What FPGA logic do constants consume

Hello,

Suppose I have a large set of ~6000 vectors ( 16 bits each ) which I use as coefficients in my design.
There's no address decoding (each set is connected to a specific logic block) and all sets are constant during compile time.

Will these be implemented as simple wires to VCC / GND or there's a chance that the tool will use LUTs / Registers / RAM for some reason ?

They just get connected to VCC/GND

If it's appropriate to store the constants in ROM (initialized RAM), you can do that. The tools won't do that "for some reason" rather than your decision.

If it's appropriate to store the constants in ROM (initialized RAM), you can do that.

Click to expand...

I don't want to do that.
I need all values to be accessible simultaneously and (obviously) would prefer it consumes no resources other then routing to VCC / GND.

Again,
I have a large array of N vectors and N circuits.
Each vector is connected to a different circuit.
The vectors are all constant during compile time.

Intuitively, I see no reason why these constant vectors shall be implemented by something other than simple wires to either VCC or GND.
And this is exactly what I want...but I'm not 100% sure.

Do you agree that that's what would happen ?

Why not compile the design, and take a look?

I need all values to be accessible simultaneously and (obviously) would prefer it consumes no resources other then routing to VCC / GND.

Click to expand...

Why did you ask about RAM then?

You'll surely get GND/VCC wires in RTL netlist. During synthesis, all possible logic minimizations will be made, pulling the constants into the logic terms. (Unless the logic blocks are locked).

TrickyDicky said:

They just get connected to VCC/GND

Click to expand...

Not really, it is more complicated than that. You don't want to have any logic lumped to the ground/vdd wires as they would bounce a lot. You'd typically provide a constant that comes from a special gate called tiecell. There are cells for tie high and tie low. The FPGA vendor might hide that from you, but internally that is how it works.

ThisIsNotSam said:

Not really, it is more complicated than that. You don't want to have any logic lumped to the ground/vdd wires as they would bounce a lot. You'd typically provide a constant that comes from a special gate called tiecell. There are cells for tie high and tie low. The FPGA vendor might hide that from you, but internally that is how it works.

Click to expand...

Exactly this....

Shown implemented in Vivado like this: