what does this verilog HDL statement mean?

[ls00722]

Hi:
I am a beginner on VerilogHDL, what does the following statement do?

reg sum_out_shift[25:0];
reg sum_out_sat[7:0];

sum_out_shift <= {{18{sum_out_sat[7]}}, sum_out_sat};

Sign extending the sum_out_sat? Why "<=" sign was used , not the "=" sign?

Thanks
chris

 

[RBB]

Google blocking vs. non-blocking statements in Verilog...

https://www.google.com/webhp#hl=en&source=hp&q=blocking+vs+non-blocking+in+verilog

 

[jakov]

Maybe this answer: **broken link removed** is useful.

 

[Jack// ani]

Go through this paper, by all means best one of its kind:

http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

 

[mux_master]

Yeah it is sign extending it. The 18{sum_out_sat[7]} replicates the MSB of sum_out_sat 18 times. It is then concatenated with the other 8 bits for a total of 26 bits. This is consistent with the length of sum_out_shit. The <= is the non blocking assignment and the = is the blocking assignment.