What does this error mean when trying to Optimize a PLD design?

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I am trying to build an old PLD design for a XC7300 chip using Xilinx Foundation 1.3 (time limited version).

All I have for the existing design is an Abel file and I need to build a Intel Hex file to program a chip.

The Flow Engine seems to translate the Abel file ok.





Next I tried to run the Optimizer but it fails with an error message:





The project and design files are attached. Anyone have any idea why the optimizer is failing with that error message?
 

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  • RAMROMF1.zip
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Interesting post in an era when people are already migrating designs from Series6 to Series7 FPGAs. I am sure you have an important motivation there.
 

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