Re: retiming
Major (read all) :wink: of the synthesis tools like XST, Synplify Pro. support retiming..
Excerpt from Xilinx Synthesis Technology (XST) User Guide..
"Retiming is a technique that consists of moving flip-flops
and latches across logic for the purpose of improving timing, and so
increasing clock frequency.Flip-flop retiming can be either forward
or backward. Forward retiming will move a set of flip-flops that are
the input of a LUT to a single flip-flop at its output. Backward
retiming will move a flip-flop that is at the output of a LUT to a set of
flip-flops at its input. Flip-flop retiming can significantly increase the
number of flip-flops in the design, and it may remove some flip-flops.
Nevertheless, the behavior of the designs remains the same. Only
timing delays will be modified...."
Excerpt From Synplify Pro User Guide..
"syn_allow_retiming
Attribute; Xilinx and Altera. The syn_allow_retiming attribute determines
whether registers may be moved across combinatorial logic to improve
performance in Xilinx Virtex and Altera APEX, APEX II, FLEX10K, Excalibur,
and Mercury architectures..."
Hope it helps..
tut..