Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What does the retiming feature do in synthesis tools?

Status
Not open for further replies.

vaf20

Full Member level 3
Joined
Jan 27, 2003
Messages
174
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
1,479
hi
what's this feature in synthesis tools?
gracias
 

retiring

Retiming is the mechanism to optimized your fpga design in terms of timing issues such as clock skew, race condition, slack and etc.
 

Re: retiming

hi again
which synthesis tools have this feature
tnx
 

Re: retiming

Major (read all) :wink: of the synthesis tools like XST, Synplify Pro. support retiming..

Excerpt from Xilinx Synthesis Technology (XST) User Guide..

"Retiming is a technique that consists of moving flip-flops
and latches across logic for the purpose of improving timing, and so
increasing clock frequency.Flip-flop retiming can be either forward
or backward. Forward retiming will move a set of flip-flops that are
the input of a LUT to a single flip-flop at its output. Backward
retiming will move a flip-flop that is at the output of a LUT to a set of
flip-flops at its input. Flip-flop retiming can significantly increase the
number of flip-flops in the design, and it may remove some flip-flops.
Nevertheless, the behavior of the designs remains the same. Only
timing delays will be modified...."

Excerpt From Synplify Pro User Guide..

"syn_allow_retiming
Attribute; Xilinx and Altera. The syn_allow_retiming attribute determines
whether registers may be moved across combinatorial logic to improve
performance in Xilinx Virtex and Altera APEX, APEX II, FLEX10K, Excalibur,
and Mercury architectures..."

Hope it helps.. :)
tut..
 

retiming

If you have time, check the "VLSI DSP Systems" by Parhi, one of the book's chapter named "Retiming".

Retiming is to change the locations of the Delay Elements (D-FF) and not to change the timing characristics of the circuit.

I think retiming is useful when your chip lack of D-FF resoures, if you use FPGA, it may useless (for FPGA has so many D-FF 8)).

Bye,

Davy Zhu
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top