What does mean XY in Xilinx FPGAs? (UCF problem)

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Hi,

What does mean X0Y4 in this code?
Code: 
INST "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y4;

I usually find locations in the "Packaging and Pinout Specification" document. But there is nothing about X and Y like this! How can I find XY?

Thanks in advnace
 

It's an internal FPGA resource location constraint which has nothing to do with pinout. You'll find it e.g. in a chip floorplanner tool.
 
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    spman

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Thanks FvM.

How can I find the GTP transceiver corresponding to specific IOs in PlanAhead?
 

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