What does mean XY in Xilinx FPGAs? (UCF problem)

[spman]

Hi,

What does mean X0Y4 in this code?

INST "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y4;

I usually find locations in the "Packaging and Pinout Specification" document. But there is nothing about X and Y like this! How can I find XY?

Thanks in advnace

 

[FvM]

It's an internal FPGA resource location constraint which has nothing to do with pinout. You'll find it e.g. in a chip floorplanner tool.

 

[spman]

Thanks FvM.

How can I find the GTP transceiver corresponding to specific IOs in PlanAhead?