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PLI stands for Programming Language Interface. Is a macro language to use in Verilog sources for simulation purposes (text I/O etc).
This is one of the main reasons that Verilog sucks (personal quote). You need two languages (Verilog and PLI) for writing efficient proggies in Verilog! Good refs are: Celia C. page, and at www.eda.org.
FLI: Foreign Language Interface. Is some proprietary macro language by ModelSim. Supposedly for cosimulation of "foreign" language modules with VHDL or Verilog. E.g. you have a bus functional model of a peripheral in C and you want to simulate it in conjunction with your VHDL core.