The output is just fine as shown in the following image,
It works as desired but I don't understand what the symbol "#" do. The symbol makes no difference.
It is used in the OpenBTS project in many positions so I need to know what does i do.
Hi,
I dunno what do they use it allover the design files. I think having so many "#" inside the design files gives the impression of "spaghetti" coding, although the code is very well structured.
I have seen some coding styles that require some small delay in them to simulate correctly, because without the delay a race condition will ensue and the simulation will not be correct. Looking at the code above, I can see why the delay might be necessary. Each element of the pipeline is loaded with the previous element using a non-blocking statement. Without the delay, each stage of the would be loaded simultaneously in simulation and there is a chance the simulator will not reflect what is supposed to happen.
Without the delay, each stage of the would be loaded simultaneously in simulation and there is a chance the simulator will not reflect what is supposed to happen.
May be the author of the code was stuck in the same misunderstanding of Verilog behaviour. Actually the evaluation rules for non-blocking statement will be sufficient to achieve correct behaviour of the pipeline construct. The LHS of the assignment will be updated at the end of the clock cycle, after the iteration and the always block have completed.
---------- Post added at 18:18 ---------- Previous post was at 18:06 ----------
Can u please give an example for the use of "#" for synthesis..
However, it is still true that I have had the displeasure of using and debugging supposedly synthesizeable code which did not simulate correctly without benefit of small delays. Debugging usually meant rewriting.
Standard simulation is functional simulation, where all logic element delays are ignored. Simulation of synchronous designs should regularly work without auxilary delay statements. External interfaces and modelling of periperals devices may require it, also stimulus generation of course. Personally I never used delay statements in the design or unit under test, only in the testbench itself and simulation models.