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What does Code Coverage mean ?

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Advanced Member level 4
Jan 6, 2003
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Hi folks ..

What does Code Coverage mean ? .. what tools are used to do that ? .. and is it only one kind of coverage or there are more than one ? .. like in DFT for example we have BIST and Scan Chains and so on .. all for DFT .. is it something like this in Coverage ?

code coverage is the metric that tells you how much percentage of your design code have you covered (executed) using your testbench, during verification.

Code coverage covers the following metrics :
1. Statement coverage (whether you have covered all your active statements)
2. Expression coverage (whether you have covered all expression possibilities)
3. Branch coverage (whether you have covered all the possible branches; as in a case loop for example)
4. Toggle coverage (whether al toggles are exercised)
5. FSM coverage (whether all the states and different possible state transitions have happened)
6. Condition coverage (whether all conditions were generated)

This collective metrics will give you an idea of the completeness of your verification. That is if you achieve 100% coverage it means yuu have verified and tested all possibilites in your design code.

Code coverage can be calculated by the simulators like modelsim, vcs or nc verilog or any standard simulator. If you enable the appropriate coverage switch the simulator will calculate the coverage and store it in a database (typically in a .db file) during the simulation of your test case. You can get the coverage report from the database file using appropriate commands. Refer the simulator user guide for those.

Apart from this you have functional coverage which was brought by HVLs like e and Vera. It measures whether all possible verification scenarios were generated and verified with the design. This needs you to write code describing the functional coverage groups. This is more difficult to achieve (100%) and 100% functional coverage will automatically achieve 100% code coverage. Functional coverage metrics gives a better idea about the completeness of ur design.


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that is fault coverage, not code coverage.

=RTL coverage
Tools are available that, given an existing RTL design and a set of vectors, will provide valuable information. Apart from learning to use the tool and spending some time understanding the reports, RTL coverage does not fundamentally change the existing methodology and therefore can be added to any design project .

The basic idea behind RTL coverage is that, if the designer wrote a line of RTL, it was meant to be useful for something. While the tool does not know what for (a limitation that we'll discuss later), it can correctly identify problems when a line was not used for anything at all.

Expression coverage looks at the right-hand side of an assignment and gives a more c omplete picture of the circumstances that cause an assignment to actually execute.

Code coverage is a metric that shows how much work you have done regarding functional verification. Note, it only indicates that you haven't done enough but never proves you have finished your work. Surecover and ICT are dominant tools.


Whatever design is there, it shud be functionally verified before implementing it in FPGA or ASIC. The percentage of this functional verification done is called code coverage. That means, entire code that is written shud be verified functionally. VLSI industry now aims at 100%(functional) code coverage and 98% testable chips.


How to define functional coverage?

Is there any formula?

functional coverage can be done only by HVLs. You hav to write coverage monitors for this. it is like u specify what all scenarios has to be covered by a bus or cross combination of many buses or signals etc. Here u hav to know and identify what all possibilities has to be covered by the verification to write the coverage monitors. ur simulator can then generate the reports (HTML or text) from the .db file.


May I know what is HVL?

I think it is very difficult to achieve 100% coverage (if not impossible). Even the possibilities you define may not actually covers all of the possibilities... Am I right?

should be possible to reach a 100% code coverage;
as said in another reply, teoretically each line of the code has been coded for a reason; with the testebench is possible to setup the correct test case to stimulate a particolar line of code.
An exception can be the lines are NEVER executed, for example, in a case statement "WHEN others => null;" but this can be handled by the tool.


I am talking about functional coverage, not code coverage. For code coverage, we check every line of the codes. But for functional coverage, we check the codes by testing all possible functions of the code(device). Functional coverage is higher level than code coverage.

Am I right?

HVL --> Hardware Verification Language, eg : Vera, e

Functional coverage is more difficult to achieve than code coverage, but 100% functional coverage is not impossible bu yes its difficult.

the possibilities that we specify should have all legal possibilities. Some situations may be possible but illegal or which are highly improbable in a real time environment.

i agree with that

Added after 1 minutes:


hi, currently i'm also confused about whether the code coverage in RTL shall be adopted and i'd like to know how many of you have utilized it and what effect it will put on your robustness of your RTL codes?


code coverage does not help in improving the robustness of ur RTL, rather it helps in chacking the completeness of ur verification process. It tells u whether u hav tested all lines and possibilities presentin ur RTL. If u hav tested all possibilities in ur RTL u get 100% code coverage and u can be more confident of ur RTL being bug free.

In HDLSCORE: code coverage is listed below
1. Block coverage. which is symbolic by begin ... end implicitly or explicitly
2. Expression coverage.
3. Path coverage
4. Toggle coverage
5. FSM coverage

Hope it's useful to u.

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