dear all,
when i run synthesize for my VHDL code and check its RTL schematic on ISE6.2i i found some blocks called 'ALIAS', does that mean anything wrong?
thnks for ur help, but when i synthesize it on ISE of xilinix i found that alias
anyway, i need u to check this code for me too, as i got same problems with it
As I don't have a RAR program handy at the moment, I looked at the Word file. There is nothing wrong with the ALIAS signals. What you're getting is normal.
An "alias" is an alternate name. The RTL circuit is an FSM. The signals don't correspond to VHDL signal names. The name of the signal is actually the name of an enumeration that was used to define a state in the HDL code.
For example, if you define several states:
type dev_state is (idle, run, done);
then VHDL defines idle, run, and done as constants - not signals.
The synthesizer infers from your coding style that these constants are being used to drive an FSM, and they are translated into actual signals with an assumed name (an alias), which is the same as the state name.