What does affect to clock gating or scan cell insertion on hvt , rvt library?

[u24c02]

Hi
I'm trying to implement with design compiler.
I just wondering about affect on hvt, rvt to scan or clock insertion.
What is the best method which used library when scan and clock insertion?

I usually used as follows.

1.target library read only rvt
2.read verilog
3.compile
4.re target library set with rvt hvt
5.re compile with scan and clock gating insertion.

 

[artmalik]

I think you have to think in a different way....depending on how you start....if you start with rvt most of the flops the flops will be rvt....so when you enable hvt ...not all the rvt will be converted to hvt (if your design can meet timing with hvt).

Synthesis is usually done with faster library like rvt if the speed is high while hvt if power is main concern. You should try with hvt first and if you are able to meet timing the tool will take care of the rest. The choice of target library depends on the speed you are trying to achieve.

 

[u24c02]

Thanks sir,
I think, maybe if we have done with only hvt to timing meet. Then this would be the best way as your said.
What if we have some problem while synthesis then we consider rvt.

 

[artmalik]

I don't see any issue with any approach ...if you start from rvt : your leakage will be high and cell drives might be higher...also the cell count will be different.... there is no issue with rvt or hvt...it is question how power consumption, area, tradeoff... it is QOR which you are interested in will determine the choice

 

[u24c02]

Thanks sir