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If it's from the documentation for the Xilinx memory cores, it is a shorthand way of referring to ports ADDRA[m:0] or ADDRB[m:0].
It gives a variable for the upper index of the bus because that is, of course, configurable by you. ADDRA could be 2 bits wide (m = 1, or [1:0]) or it could be 64 bits wide (m=63, or [63:0])
You probably saw this on a table in the core documentation that has the typical port list for your selected core.
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