what does a pcb layout tool should know to generate traces (working freq....)?

[hfss_newbie]

what does a pcb layout designer should know to generate traces (working freq....)?

Hi guys,

I've never done any PCB routing so my question maybe seems quite silly.
Here is the Normal step of pcb layout manufacturing from my understand:

I design a simple microstrip pcb with several layers with two discrete active components (Microcontroller and memory RAM for example) both sides of pcb traces for a working freq. off0 with one of EDA tools (such as Agilent ADS) so microstrips length have been calcluated in simulation and characteristic impedance and dielectric loss have been taken into account.

For pcb layout design, if these two components exist in EDA vendor component libraries (e.x. ADS libraries) then we have physical information of these components (package size, pin(footprint)size) AND input/output impedance of these components pins (socket interface) in that freq f0.

thanks to the pcb layout editing tool inside EDA, i can generate the layout and export it to a gerber file format and i'm done but it seems to me that cross-talk is not taken into account in the pcb layout tool.
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Here is the current situation in which i don't have access to any EDA.
I have
1- both components physical information (i have bought them).
2-the input/output impedance of these components pins at my working freq. f0.
3- the working freq f0,
4-the dielectric and copper info. which gives characteristic impedance of the pcb layout that i want someone to generate for me.

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A-Does EDA pcb layout tool need more information than these 4 above info to create traces (create a gerbor format file)?

As i said in my company they don't have any EDA tool and they didn't do any shematic capture and simulation. They bought these two components. they localized their positions on a future pcb and asked a router designer person to attach these two components.
I think that the router designer, does the samething that an EDA pcb layout tool does except that he doesn't know the microstrip trace length that we obtain from simulation when we have an EDA.


the router designer will use a good geometric algorithm (software tool) to create traces as short as it's possible.with a high quality dielectric and copper, he can amost omit the dielectric losses that his traces length (which can be longer or shorter than of the simulation length) add. but he can never omit the phase shift that he adds by using longer traces.so

B-How can a a router design person route traces on a pcb and ignore the problem of phase shift?

C-Does EDA pcb layout tool in EDA uses schematic and simulation tools results to geneate a layout?

D-Do we have tools that are just PCB layout tools and don't have the other tools (schematics tool,simulation tool) of an EDA?


sorry if it's a very long thread. and thanks very much for any comment.

 

[barry]

If you know the board stackup (copper and laminate thicknesses) and dielectric constant, you then can calculate the required trace width and apply that width constraint to your traces. At least, that's what I do using PADS Layout.

 

[hfss_newbie]

Barry thanks very much,could you please kindly rephrase your answer?
or if you can answer my alphabetical questions?

 

[FvM]

Usual PCB tools are operating with electrical netlists and mechanical information (footprints, pcb layer stackup, trace routing). They don't care for impedances, substrate permittivity, signal frequencies and such.

A PCB tool might provide an interface to a SI(signal integrity) tool or an EM simulator.

 

[barry]

Barry thanks very much,could you please kindly rephrase your answer?
or if you can answer my alphabetical questions?

Maybe you could rephrase your questions, they are all over the place. First you're asking about frequency response and impedances, then you are asking about whether schematic capture comes bundled with the layout tool. Ok, I'll try.

A) Answered in post #2
B) You can't ignore phase shift (I assume you mean propagation delay)
C) No.
D) Yes.

 

[hfss_newbie]

Usual PCB tools are operating with electrical netlists and mechanical information (footprints, pcb layer stackup, trace routing). They don't care for impedances, substrate permittivity, signal frequencies and such.

A PCB tool might provide an interface to a SI(signal integrity) tool or an EM simulator.

So a PCB tool such as layout print tool of Agilent ADS(EDA) provides an interface to ADS simulation tool meaning that I can export layout tool output file output to ADS simulation tool or to an EM simulator such as HFSS.Am I right?
I have once used ADS and schematic tool, simulation tool and layout tool are bundled together.

Thanks again

- - - Updated - - -

Maybe you could rephrase your questions, they are all over the place. First you're asking about frequency response and impedances, then you are asking about whether schematic capture comes bundled with the layout tool. Ok, I'll try.

A) Answered in post #2
B) You can't ignore phase shift (I assume you mean propagation delay)
C) No.
D) Yes.

Regarding your response to question B:
If the router designer doesn't care about my board working freq.(as FvM stated) he doesn't know without simulation that adding 2mm more to the traces will add X degrees propagation delay to my signal.
If you're the pcb router designer and i give you this spec(1-my 2 components exact position on the board, 2-the PCB stack up, 3-the trace width i require(for impedance matching) in my understand this spec. is not enough. because you by adding trace lengths more than what comes from simulation(which you don't know) you add propagation delay and since the signals are not IDEALY pulse-shaped, they have other freq. components which will be propagated with different speed on this traces, so it will create overshooting and undershooting to my signal in terminal.
but you as a router designer use the trace lengths close to one i've simulated(which you don't know) , we can be sure that these overshoot-undershoot have been taken care in simulation so no worry.

That's what comes to my mind, form SI theory but as I said i'm completely ignorant to tools and what they need to work.


Thank you again

 

[marce]

If your boards are that critical then they need to be designed by someone with high speed layout experience and SIV tools. You tend to lay the board out using constraints then check the results with simulation, you can add skew groups etc, but from what you describe it sounds like you are applying to many restrictions on the layout at the initial stage, possibly making it impossible to lay out.

 

[FvM]

If the router designer doesn't care about my board working freq.(as FvM stated) he doesn't know without simulation that adding 2mm more to the traces will add X degrees propagation delay to my signal.

An advanced (auto) router tool has e.g. constraints for trace length and length matching, crosstalk in terms of critical traces spacing and allowed parallelism, preferred routing layers, signal screening, maximum via count. But it doesn't automatically translate electrical specifications and board parameters into geometrical rules. That's the job of an experienced PCB designer.

 

[marce]

And an engineer to guide him.