May 7, 2012 #1 T the moon is back Member level 2 Joined Apr 29, 2012 Messages 42 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,566 hi, when i simulate some digital design using vhdl on xlinx, in synthesis report it shows that this much of slices have been used. basically what is s slice?
hi, when i simulate some digital design using vhdl on xlinx, in synthesis report it shows that this much of slices have been used. basically what is s slice?
May 7, 2012 #2 X xtcx Advanced Member level 1 Joined Dec 22, 2007 Messages 493 Helped 65 Reputation 130 Reaction score 58 Trophy points 1,308 Location Bangalore, India Activity points 5,003 1 Slice = 4 LUTs (Lookup tables) for Virtex-5. or sometimes just 2 LUTs for Virtex-4. This might change based on chips.. http://www.1-core.com/library/digital/fpga-logic-cells/ See this
1 Slice = 4 LUTs (Lookup tables) for Virtex-5. or sometimes just 2 LUTs for Virtex-4. This might change based on chips.. http://www.1-core.com/library/digital/fpga-logic-cells/ See this