What could be the reason for PLL not locking?

[shiv_emf]

what could be possible reasons?

 

[Old Nick]

Re: pll is not locking !

Check power pins are at the correct voltage.

other than that it'll be the values of the components you have picked.

don't apply an input frequency, and look at the output of the VCO to see what frequency it is sitting at. Chenge some external components untill the VSO rests at the frequency you require it to be at.

 

[FvM]

Re: pll is not locking !

Without guessing, I just can say: It depends on the PLL.

 

[sunjimmy]

pll is not locking !

Could you specify what kind of PLL you use?
Where does this PLL come from? In-house design or external IP??
If possible, plz specify what kind of waveform you observe during characterization??

 

[wkong_zhu]

pll is not locking !

Maybe your input reference clock frequency is out of range.

 

[shiv_emf]

pll is not locking !

its an external Ip( line lock pll)
Spec has just given 54.1 reference clk freq. im using 50Mhz.
will it cause any prob?

 

[jecyhale]

Re: pll is not locking !

what could be possible reasons?

Maybe the loop filter is not suit for your pll.

 

[mouzid]

pll is not locking !

Perhaps the Frequency divider is not able to divide the VCO signal.

 

[FvM]

Re: pll is not locking !

The lock range may be too low to tolerate 50 instead of 54.1 MHz. Normally I would expect an IP core to be parametrizable for different reference clocks, if technical possible. But you could use a test generator with variable frequency to see if the PLL locks at all.