I think you have multiple VSS power in your design? If yes you have to use psub2 layer to isolate it because physically, all the VSS will be sharing the same node- psub for single well process.
Hi there I have encountered that problem. To fix it you have to make sure that all your substrate connection should be tied properly...no floating substrate for sure.
Which mean that you have to double/triple check your schematic substrate connection of each devices or blocks..when you rerun your lvs the psub_stamp error will go away.
it depends on the process. all of your answers may be correct. i have an experience wherein you have to put an extra layer on some substrate on NMOS to differentiate it to other substrates. they are not connected on the same VSS. the use of the layer is to show that they must not be connected on the same VSS.
it depends on the process. all of your answers may be correct. i have an experience wherein you have to put an extra layer on some substrate on NMOS to differentiate it to other substrates. they are not connected on the same VSS. the use of the layer is to show that they must not be connected on the same VSS.
some processes use psub2 to isolate different VSS. in case you are using triple well, i think there would be no problem because you can use the second Nwell to isolate those diff power lines.
The triple well could be solve the problem but, can you use it? You should discus this with the designer.
In your layout you have Psub contact connected in different point. you can solve this error in two way:
1) find the floating contact, and connect them all togheter, if you can.
2) Use msub layer to separate them logicaly.
I have encountered this error multiple times. As the name suggests this is related to the psub taps placed in the circuit.
Make sure none of the substrate taps are floating. All of them should be connected to the right potential. This will resolve the issue.
Can somebody explain how this error is related to triple well ( I work on N-well process) ?
Psub contacts are noting but the substrate taps that you place for the nmos transistors. When there are multiple taps in thelayout, it is quite posible that you miss out on the connection of any of these to the desired rail(power rails for ntaps and substrate rail for ptaps).That is when these are left floating and LVS throws these Stamp errors. I hope this helps.