What are the types of IO pads?

[sandysuhy]

Hi everyone,

Is there any good book or material on IO pads.Something like pad ring , staggered pads, core limited pads etc. Can anyone help me to know about these type of pads.

Regards
Sandysuhy

 

[cheelgo]

basic esd and i/o design pdf

i also not very familar with the IO pads.
rgds
cheelgo

 

[nandu_r]

bond pad design

book name "Basic ESD and I/O Design"
author Dr Sanjay Dabral; Dr Timothy J. Maloney

Since IO cell layout development is largely influenced by the ESD issues, this is the right book
Furthur
Any I/O layout called corel limited onlyf if io layout dimention have less hight and more width
this gives more core area
in case of pad limited IO , more IOs can be placed in IO ring. So stress on less width and more hight, so number of IO that can be placed in the IO ring limited by bond pad placement.

 

[mediative]

stagger bond pad

pad can be divided to be inline pad& stagger pad.
inline pad is the most traditional type. it is often to be quadrate pad and its bonding pad is located in the terminal.
stagger pad comprise short stagger and long stagger and its bonding pad are stagger format.
The two types pad have the use as following:
as to core limited design,we can use inline pad putting erect to decrease to die size.
as to pad limited design, we can not all use inline pad avoiding being a great the die size .we should use stagger pad to decrease the die size.
Anywhy, the chosing of the type of the pad are considering to decreasing the die size. there are no function difference between them,moreover the stagger pad is more difficult for the backend design.

 

[tarkyss]

io layout

nandu_r
do you have the book?

 

[Kulprashant]

io ＆ core pad

Hi all,
how to place IO PADS using P&R tool in ASIC Design?
In my gatelevel netlist IO PADS information is not present so is it necessery that gatelevel netlist should contain IO PADS information? if yes what r parameters to be given while doing RTL synthesis in ASIC flow.

prashant

 

[sathi.ec]

stagger pad

Hi
Kulprashant

I don't no in ASIC design, But i am working in TANNER tool, in that one we just goto cell instance in the LAYOUT view and browse the LIBRARY and place it where ever u want.
After place n route, The gatelevel netlist should have the IOpad details, Because after Package we will going to apply signals to the PADs only. so, gatelevel netlist should have some information about IOpads.


sandysuhy

I don't no the Text book, but i have a pdf file of IOhandbook. i have attached here.

Sathi

 

[funzero]

staggered pad power

but still can you suggest me a good book on how to arrange pad.
and how to define pad ring acroding to design spec.

 

[anjali]

i/o pad layout

book name "Basic ESD and I/O Design"
author Dr Sanjay Dabral; Dr Timothy J. Maloney

Since IO cell layout development is largely influenced by the ESD issues, this is the right book
Furthur
Any I/O layout called corel limited onlyf if io layout dimention have less hight and more width
this gives more core area
in case of pad limited IO , more IOs can be placed in IO ring. So stress on less width and more hight, so number of IO that can be placed in the IO ring limited by bond pad placement.

i think core limited means, core area requirement is more & pads can be easily placed & sometimes there can be gap between the io pads. that time, filler pads need to be used for continuity. then, why HEIGHT & WIDTH is comming in to picture. actually it is regarding to area. please clarify me.

Added after 39 seconds:

book name "Basic ESD and I/O Design"
author Dr Sanjay Dabral; Dr Timothy J. Maloney

Since IO cell layout development is largely influenced by the ESD issues, this is the right book
Furthur
Any I/O layout called corel limited onlyf if io layout dimention have less hight and more width
this gives more core area
in case of pad limited IO , more IOs can be placed in IO ring. So stress on less width and more hight, so number of IO that can be placed in the IO ring limited by bond pad placement.

i think core limited means, core area requirement is more & pads can be easily placed & sometimes there can be gap between the io pads. that time, filler pads need to be used for continuity. then, why HEIGHT & WIDTH is comming in to picture. actually it is regarding to area. please clarify me.

 

[clj023]

basic esd and i/o design sanjay dabral

i agree with anjali
In addtion, the ESD layout of I/O pad is very important also which may be requied by custom.

 

[oxford]

type of i/o pads

The more details about ESD and PAD is
required, who can tell more?

 

[kumarans]

staggered pad

Hello every one,
The Pad placement is done according the power placement, the resisitance comes in picture to place the pad so considering all the constrain the IO ring will be formed
Rgds
Kumaran.S