Re: static timing analyis
To resolve timng violations, you need to carefully analysis the STA report to find the reason that cause the violation. Typically, the reasons are:
1. Inproper constraints at module level. If you use a bottom-up compile methodology, it very likely that when you compile at module level, timing budget is not correct, and the problem raise when you stitch them up at top level. A top level incremental compile can normal resolve this, but sometimes, the design is too big to fit into an incremental compile.
2. Snake path. This typically caused by your design is not correctly partitioned.