One issue is that the design is more sensitive to duty ratio variations. eg, if the clock is spec'd for a 40/60 to 60/40 ratio, the design will need to essentially be able to meet more than a 2x clock rate. eg, a perfect 50/50 clock would have paths requirements of 1/2 the clock period. a 60/40 clock would have some paths that are easier to meet (6/10th of a clock period) and some that are more difficult (4/10ths). if the range spans from 40/60 to 60/40, then all paths would need to meet 4/10ths of a clock period, which would mean the circuit could support a clock rate 10/4ths as high. (2.5x).
It also requires more design effort, as you would need to be careful with the transfers of rising to rising, falling to falling, rising to falling, and falling to rising.
Existing IP likely makes use of a single clock. The use of both clock edges over a 2x clock may make it more difficult to interconnect to existing IP.