Re: designing of FIFO
Hi,
The first thing you need to consider is the depth of the fifo.This is determined by the read and the write speed(Its the ratio).
Since this is a synchronous fifo, so managing read and write pointers for accesing the fifo is not a tough job. Remember, write pointer will point to the next location being written and read pointer points to the location being read.
Now there will be some signal controlling the read and write access to the fifo.
Whenever the write signal is asserted, write the incomming data to location pointed by write pointer and then increment the pointer.Whenever the read signal is asserted, read the data pointed by read pointer and increment the pointer.
To generate the control signals life fifo full/empty/overrun/underrun compare the read and write pointers.To prevent more than one bit change, use gray encoding for the pointers.
Hope i was clear above.
Regards.
dak-ju