Re: low power design
well there ae three levels of achieving low power
RTL level
architectural level
algorithmic level
most popular is the algorithmic level of achieving low power.
there are some methods like
clock gating
signal gating
reduting switching activity - transistor sizing, progressive transistor sizing, input reordering, time multiplexing resources and logic restructing.
adiabatic computing - reduce the voltage swings
dynamic voltage scaling - reduce the threshold voltageuse of low power busses - low sing busses..
reducing the voltage swing can help us reduce the power consumed.
these are a few ways to achieve low power of operation.
with regards,