Re: Making a Chip
The chip design process begins with the architecture design. Once the architecture and operating frequencies are determined, the next step involved is to write the RTL for that. The verification stage takes care of the potential bugs while the RTL is written. DFT is another part thats incorporated in the RTL, so that the design can be tested post fabrication. Once the RTL is completed, the timing information is created by creating the constraints file. Then the RTL is synthesised to create the netlist. Once we have the netlist and the constraints available, the physical design flow starts. The PD flow acn be summarised has having the following steps
1. Library Creation
2. Design Import
3. Floorplanning
4. Power planning
5. Placement
6. Clock Tree synthesis
7. Timing closure
8. Routing
9. Extraction
10. Crosstalk analysis
11. Signoff STA
12. Physical verification - DRC, LVS, Antenna
The design which is written out in a standard file format (GDS) is provided to the fab for fabrication. Once the fabrication and packaging is done, the chip is available for testing. If the testing is clean, its ready for large scale production.