What are the inputs required to do post layout timing analysis and for power analysis

[n.suresh60]

Hi Friends. I hope all of you doing Well.

Please mention what are the input files required for the Post layout STA, and for the Power analysis.
like what are the library files required or any other file..and how to do power analysis with Cadence EPS tool- what are the input file required to do power analysis.?

Thank you..

 

[yuhiub90]

Re: What are the inputs required to do post layout timing analysis and for power ****

Post layout STA requires gate level netlist, stdcell timing library (lib or db) for cell delay. SDF or SPEF for interconnect delay. Design contraints (SDC from SNPS).