What are the factors that increase Clock Path Skew?

[choonlle]

Clock Path skew is caused by placement between source (FF) and destination(FF). Beside placement bet. FFs, is there any factor will increase clock path skew?

 

[Iouri]

Clock Path Skew

clock skew is determinated by your clock network and delays what can occures in the PLLs

 

[Iptuous]

Clock Path Skew

the routing will determine the skew as well as the placement

 

[sachingorkhe]

Clock Path Skew

Any buffers within the clock paths could also increase your skew to destination FFs.