What are the effects of fingering?

[varunmjman]

I am designing a folded cascode OTA. The tail current of the differential amplifier is created using a PMOS transistor of size 120/0.7um. In the intial state no fingering was applied. The design was carried out for a current of 140uA. But later for the layout the number of fingers were changed to 40. This time the current dropped down to 120uA. Does the drain current changes by applying fingering and why???

plzz help me...

 

[ieropsaltic]

fingering effect

Due to second order effects, current may not change linearly with W/L.

Sometimes the effect of the STI can cause also current to change. STI stands for Shallow Trench Isolation, which is the way used to isolate the MOS device. It's performed by removing part of the substrate and applying oxide in this part. This ,however, causes stresses on the device altering its physics. When a single finger is used, the whole device suffers from the STI effect, but when fingers are used, only the outer fingers suffer from STI, while other fingers are shielded by the outer ones.

 

[dalraist]

after effects of fingering

Moreover, the silicide formation on the 2 configurations is different, resulting on 2 different resintance on Source and Drain terminals.

 

[JoannesPaulus]

tell me how finguring is done?

Did you use fingers for the diode connected pmos as well? Moreover, if your diode connected transistor is a, let's say, 4-finger device, it is good practice to layout the mirror in 4-finger groups, adding dummies if the two devices are not multiple of each other.

 

[timof]

effect of fingering in layout

I am designing a folded cascode OTA. The tail current of the differential amplifier is created using a PMOS transistor of size 120/0.7um. In the intial state no fingering was applied. The design was carried out for a current of 140uA. But later for the layout the number of fingers were changed to 40. This time the current dropped down to 120uA. Does the drain current changes by applying fingering and why???

plzz help me...

Are these current values obtained from measurements or from simulations?
What technology node are you using?

The difference may be caused by metallization, which will have different layouts for these two cases.

The fingering is done to improve device characteristics - to reduce gate resistance (important for high-frequency applications), to reduce gate-to-contact capacitances (for shared source-drain architecture), to reduce metallization resistance, etc.

Please note that popular parasitic extraction tools may not be capturing distributed effects accurately.

 

[leo_o2]

fingering

I think it might be caused by delta W. For every finger, there is a fixed delta W for simulation model.

 

[raduga_in]

effects from fingering..

What technology you are using for this design ?