What are the different techniques for fixing max-tran violations?

[designer_ec]

Hi anybody clarify fallowing doubts elaborately

1.when max transition violation occur,I mean different reasons for occuring max tran violations? what are the different techniques to fix max tran violations?
2simmilarly like above describe elaborately for max cap violation and max fanout violation.I mean different reasons and different techniques for fixing.


Thanks in advance.

 

[srkumar81]

Re: DRV

Generally for max-tran violations buffers are added after the gate which screws up the slew. max-cap violation is generally caused when the load is more. it is solved by inserting tree of buffers so that each buffer can handle balanced load. This is the method I know. If there is some more methods please let me know.

 

[leeenghan]

DRV

Hi,

Assuming that the std cell library is okay, reason of DRV can be

1. Congestion. Rotuing are detoured, or cells are shifted far away during physical synthesis

2. Optimized in one mode without visibility of the other mod (e.g. scan enable may not be visable in fn mode). Hence, some signals can be weakly driven and can cause drv with small changes (e.g. buffer added during CTS)

3. cross-talk noise. Routing cap inceases.

There are others, but I think we know what is it when you see it happen.

Regards,
Eng Han

 

[xinsu]

DRV

normally,most of DRV can be fixed by optdesign,and you can move cell/add buffer or change route wirs that tool can't opt

 

[ivlsi]

Re: DRV

normally,most of DRV can be fixed by optdesign,and you can move cell/add buffer or change route wirs that tool can't opt

What is DRV?