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Overview
The proliferation of high performance 32- and 64-bit RISC processors have been a boon to designers of next generation systems in digital consumer electronics, information appliances, set-top boxes, and office automation applications. With new design methodologies and advances in manufacturing processes, powerful RISC processors can now be easily integrated into a variety of custom ASICs. But with this new capability, comes the traditional burden of providing effective debug and development tools.
On the one hand, the powerful software and development tools that come with the MIPS RISC 32-bit and 64-bit processor architecture, such as highly optimized compilers and integrated development environments, and modular real-time operating systems software make software development easier. But, unlike traditional workstation or PC-oriented application software that executes in the same platform in which the software is developed, embedded system software will execute on a separate target system with extremely limited memory and I/O resources. Debugging and hardware/software integration can become a significant hurdle to fast prototype development and ultimately to hitting the market opportunity window.
MIPS Technologies, Inc. and the MIPS architecture licensees have developed the industry?s broadest range of new 32-bit and 64-bit processor implementations spanning the spectrum of price, performance and on-chip peripheral options. Through the MIPS semiconductor licensees, system OEMs can choose an appropriate processor configuration and select from a wide variety of peripheral options. They can then quickly incorporate that design into custom ASICs that provide the optimum power consumption and compact size for their application.
But, how do you quickly and inexpensively debug a one-of-a-kind system-on-chip? Typically, hardware development tools lag the appearance of new generation architectures by a significant amount of time and generally only follow when there is a large design community. When you are designing a one-of-a-kind system, you need a more immediate option.
MIPS Technologies, Inc. and the MIPS RISC consortium have developed a specialized hardware debug technology called MIPS EJTAG. EJTAG is inexpensive, easy to implement and provides non-intrusive debug capabilities for any MIPS RISC processor system-on-a-chip that incorporates it. It has been published for use as an industry-wide standard and is documented in the MIPS Licensees, MIPS EJTAG Debug Solution, Ver. 2.0 document available from MIPS Technologies, Inc. and other MIPS RISC licensees. Beyond specifications, EJTAG is being implemented in several new MIPS processors including the TinyRISC family from LSI Logic the TX49 family from Toshiba and the JADE 32-bit processor cores from MIPS Technologies, Inc.
EJTAG Re-Uses IEEE JTAG Boundary Scan Pins for Basic Debug Interface
To keep on-chip costs low, and to minimize any target system overhead, the MIPS EJTAG utilizes the widely used IEEE JTAG pins for its debug functions. Using special debug circuitry on-chip, the EJTAG provides run control, breakpoints on both data and instructions, real-time Program Counter trace. In addition, individual licensees can add additional features when desired. Such features could include complex breakpoints and execution profiling features.
On-chip debug provides some new tools for debugging embedded CPUs that avoid the limitations of traditional hardware debug tools. For example, it is not possible to use a logic analyzer to track operations that take place between the CPU and the on-chip data and instruction caches. But, on-chip EJTAG can track these operations. Also, using In-Circuit Emulators with high speed systems is often problematical because they affect the bus loading characteristics of the system and can induce "tool-related" bugs into the system. In addition, they are rarely available for on-of-a-kind system-on-a-chip. Finally, some solutions require special bond-out chips that provide extra control signals and busses. But, this is additional design overhead in both chip and board design and it adds more precious time to the product cycle. EJTAG obtains the same results without the additional time and cost.
EJTAG utilizes the 5-pin IEEE 1149.1 JTAG specification for off-chip communications. These signals, called the Test Access Port or TAP include TRST (reset), TCK (clock), TMS (Test Mode Select), TDI (Data In) and TDO (Data Out). Internally as shown in Figure 1, EJTAG provides for a set of instruction, data and control registers and circuitry to access the address and data busses.
iransatforum, thanks for information. But I didn't understand why nand_gates consider that JTAG is "the subset of EJTAG". IMHO, JTAG is more general notion than EJTAG. At first, I suppose that EJTAG was developed later than JTAG. And also it seems for me that EJTAG specification is based on JTAG, but not vice versa. Moreover, followed from picture in your post, EJTAG circuitry consists of a standard JTAG circuit and some additional mechanisms of getting access to memory and processor registers. In principle there is nothing fundamental new. Only standartization of using JTAG in processors applications.
However, I had so little time for detailed examination of all info now. So I can be wrong.
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