Memorry BIST requirement is tightly couple to your design hence area/speed estimates from other designs won't be of much help. Area and timing are dependednt on BIST placement and the technology used fro the design. You need to pland and structure the memory bist to meet your requirement. mbistarchitect from mentor lets you explore carious configuration whether you choose serial/parallel bist
1. Usually the freq on which bist would work at will be far greater than your design, so I guess you dont have to worry about it, as the bottelneck would be your design frequecy. I would expect Bist to reach above 500MHz eaisly on 90nm TSMC library.
2. Area depends a lot on how generic ur bist engine is. Some bist engines are able to co-op with multiple memories, some are not. So area will be different in different bist engines.
Nevertheless an example here:
Gate count of a bist engine, for a memory whose address is 10 bits wide:
1635:
Library used TSMC
Technology : 90nm
Area : 10828 lib units.
I guess it would eaisly work on 500MHz+ clock speed.
Hope it helps,
Kr,
Avi http://www.vlsiip.com