Aug 8, 2011 #1 E ee1 Full Member level 2 Joined May 31, 2011 Messages 120 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,298 Activity points 2,036 can anyone list the cts main goals? and another question: when is the best stage during the asic flow to check timing in sta tool? after route? thanks!
can anyone list the cts main goals? and another question: when is the best stage during the asic flow to check timing in sta tool? after route? thanks!
Aug 8, 2011 #2 ckshivaram Advanced Member level 6 Joined Apr 21, 2008 Messages 5,060 Helped 2,150 Reputation 4,306 Reaction score 2,088 Trophy points 1,403 Location villingen (Germany) / Bangalore Activity points 30,087 The goal of CTS is to minimize skew and insertion delay check this Azuro: PowerCentric - Clock Tree Synthesis Physical Design ASIC-SoC-VLSI Design: Clock Tree Synthesis (CTS) ---------- Post added at 20:01 ---------- Previous post was at 19:58 ---------- this one for your second question http://www.newbiers.com/soft/UploadFile/digital_design/20100823/paper9_1.pdf
The goal of CTS is to minimize skew and insertion delay check this Azuro: PowerCentric - Clock Tree Synthesis Physical Design ASIC-SoC-VLSI Design: Clock Tree Synthesis (CTS) ---------- Post added at 20:01 ---------- Previous post was at 19:58 ---------- this one for your second question http://www.newbiers.com/soft/UploadFile/digital_design/20100823/paper9_1.pdf
Aug 8, 2011 #3 AdvaRes Advanced Member level 4 Joined Feb 14, 2008 Messages 1,163 Helped 113 Reputation 220 Reaction score 51 Trophy points 1,328 Location At home Activity points 7,442 The goal is to have a clock balanced circuit with a tolerable skew in the clock tree leafs.