Re: what are the challenges when porting 0.18 um design to 0
I ever referenced a design with 0.18um CMOS, then I needed to port it to the 0.13um CMOS and 90nm CMOS. In my memories, we did not not concern much about the scaled down process. We just obey the design strategy and design rules. Then it works OK.
The only concern I rember is that, in low power design, the scaled down process brings more HCE(hot carrier effect) and leakage current is more seriously.