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well tap cells are used to limit resistance between power or ground connections to wells of the substrate. taps are traditionally used so that your VDD and GND are connected to subtrate and n-wells respectively. This is to help tie them to your VDD and GND levels so that they don't drift too much (especially towards the middle of the chip) and cause latchup.
The rules for welltaps and endcaps are very technology dependent. Some technologies don't require them at all (or, the taps are built in to the std cells), and for other technologies you may need a welltap every X microns, and endcaps at the end of every std cell row. The DRC deck should flag any issues regarding welltaps/endcaps, which is one good reason to run an early DRC. You will have to consult the design rule manual for your process.
Spare cells are not required, but are usually a good idea. If you want to go back later and do a small functional ECO to your design, you can use the spare cells which are already placed around the design, and connect them with minimal mask changes (also called a metal-only ECO).
---------- Post added at 13:44 ---------- Previous post was at 13:37 ----------
so for that n tap is connected to p transistor....by connecting p tap over VDD
similarly for p tap ....is connected to n transistor....connected to VSS...