What are some effective ways to create a self checking Testbench without ref model

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Aravind_Selvaraj

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I am trying o create a TB for a certain digital design involving LUTs, Adders and memory blocks.

The requirement here is to create self checking TB without a reference model so that it improves reusability and does not require changes in RM for every minor design change.

Thanks in advance
 

The requirement here is to create self checking TB without a reference model so that it improves reusability and does not require changes in RM for every minor design change.
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What do you mean by a "reference model".

A TB should be such that it drives the DUT inputs such that the DUT functionality and stability is verified. A self checking TB should be intelligent enough to decide on the DUT outputs and generate PASS/FAIL status.
Just google 'self checking testbench' and read a couple of articles.

btw- this post should be at the FPGA or ASIC section.
 

Without some form of model, you cant create a self checking testbench. But a reference model may take one of several forms - it could be mode written in HDL, C, Matlab or any other language. It could be run in the testbench or externally. But without generating some form of expected results, you cannot have a self checking testbench.
 

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