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Exceptions are which will over ride the default single cycle path timing analysis in STA.
Exceptions are include False paths , Multicycle path and etc..
Multicycle path is a timing path, which will take more than one single cycle path. It may be due to combo logic present between FFs are more or need to delay the timing signal for some time..STA tools will analyze your setup and hold multipliers accordingly.
Mutlicycle paths are signal paths that require more than one clock cycle to propagate. You specify to the STA tool how many clock cycles you want to allow the path to get from the source clock edge to the destination clock edge.
exception is mainly include false path and multi cycle path.
false path are set for any logic which not required to analyse timing.
and multicycle path is that path which required more than one cycle compare to launch clock to execute its function
You will find a good article regarding Static Timing analysis in the below mentioned link. In this you find good articles about falsepath, multicycle path and source synchronous paths explanations and scenarios.
multicycle paths genearally requiers more time than a cycle to satisfy the setup and hold conditions ,because of large combo between the flops
false paths generally to avoid from the STA , like a path whose launch and capture of the data done by diff clocks
If launch and capture of the data done by diff clocks the path would be false path and not multicycle path. Multicycle path is For Example a slow memory access where memory access time is more then one clock