Hi Spoorthi,
I am not sure which book you are referring but they are right.
Basically in VLSI Industry we use another terminology to mention these things - Unateness.
Unateness is the property for each Timing Arc. Basically, Timing Arc is a combination of Input and output pin combination. Now as per the response, we define this property.
Like -
BUffer is Positive Unate -
Means Rising input -> Rising output or No change
Falling Input -> Falling output or No change.
In the Book sometime - it's captured as Non-Inverting.
Same you can get the point for Inverter gate.
Now, Lets talk about the AND gate.
In the 2 input AND gate - If Inputs are A & B.
When ever you make changes in A from Low to High (Means 0 to 1) - You can see that Output Either change form 0 to 1 or there will be no change in the output. This change is irrespective of value of B or change at B.
Similarly, you can see for 1->0 Transition also.
Check the Truth table, if you still has confusion.
AB Y
00 0
01 0
10 0
11 1
Like I said - for Positive Unate Timing Arc - Rising input gives Rising output or no Change. So you can see that AND gate is Non-Inverting (as per your book terminology).
Above is the direction - Now do the same mapping for Other gates and you will come to know
AND, OR, Buffer - > Non-Inverting - > Positive Unate
NAND, NOR, NOT -> Inverting -> Negative Unate
XOR, XNOR -> Neither Inverting not non-inverting - NonUnate.
You can check below article if you need more clearity.
Timing Arc
Unateness: Timing Arc