What are don't use cells?

[design_oriented]

Hi Guys,

While doing floorplanning, I came across some don't use cells like buffers and delay cells. What are these cells? At what point in the flow (synthesis/floorplanning/placement/etc) should I have them and at what point in the flow should I remove them?

Thanks.

 

[sakshi gupta]

These cells should be removed in RTL as these might cause iisues in backend

 

[design_oriented]

What problems may appear in the backend? Are these cells added later on in the backend after floorplanning?

 

[lostinxlation]

What is "these cells" ? You referred to buffer and delay buffers so you excluded other type of cells from this discussion ?

You don't need std cells to do floorplanning and also you can do floorplanning with std cells. There is no issue there except without full std cells, you have to think the locations of big macros by yourself.

 

[birdy123]

hi,
As name suggested about the "Don't use cells".. these are those cells which are present in the Library and you don't want to use those cells in your design.
More in detail:

You know when ever you are doing optimization or say using the tool like ICC for designing.. then you have to provide a technolofy library. During mapping different logic of your design with proper cell or during optimatization of your design tool uses different types of cells (standard cell/ buffer/invertor/delaycell/fillercell) etc.. present in your specific library. Since these Library is usually design independent so they have a lot of cells which are not require for a particular design.
Now If you would not like to use any particular cells because of many reason (like - driving strength,fanout,size, or your design has some specific requirement or may be some type of cells are creating problem in your design during timing closer ..etc etc) then you can mark or say set a attribute over those cells in your design as don't use cell. Now those cells will not be use in your design till the point those are like Dnt use cell.
Some time designer set few cells as dnt use cells for some part of the design and then remove those attribute later on.. or Vica versa..

So in short I can say Don't use cells are not the type of cells but these are the attributes sets on the cells and for EDA tools those become don't use cells.

I hope this helps you.
Please let me know for any further query.

 

[design_oriented]

Thanks for the help, Birdy.

I am a newbie so my questions may be stupid.

So say you dont use certain cells (buffers, fillers, etc.) during synthesis.

Can you add those cells back in during floorplanning/routing? My idea is all these dont use cells like buffers,fillers,etc. are used to achieve the given constraints (timing closure, power intent, etc.)

Does it not change the original design as you have now modified the netlist by adding these extra cells to your design? Before you tape out the final gds2 are drc and lvs the only checks to the flow to verify that the functionality has not changed?

 

[birdy123]

Hi,

yes you can use add those cells by removing the "dnt_use" attribute.
Now here you are adding extra cells but you are not changing the functionality of the design. Same with the logic also. You are not cahnging any of this. you can take this as ... lets suppose you are inserting 2 buffer in place of one buffer or Vise-Versa... now you are not changing anything here.

With respect to the DRC and LVS ... DRC is Design Rule check... It checks the design rule provided by the Foundry.Means your design is as per the recomendation or mandatory rules related to different layer rules in the design

 

[phoenixpavan]

Thanks for the help, Birdy.

I am a newbie so my questions may be stupid.

So say you dont use certain cells (buffers, fillers, etc.) during synthesis.

Can you add those cells back in during floorplanning/routing? My idea is all these dont use cells like buffers,fillers,etc. are used to achieve the given constraints (timing closure, power intent, etc.)

Does it not change the original design as you have now modified the netlist by adding these extra cells to your design? Before you tape out the final gds2 are drc and lvs the only checks to the flow to verify that the functionality has not changed?

Hi design_oriented,

Any changes in your netlist will be compiled with an incremental option and also this will be taken through a formality check to make sure that the design is as intended...so this takes care of unwanted changes being performed on your design.

DRC is as birdy indicated is not a functional check but rather a physical check. It verifies whether all the foundry rules have been adhered to or not..
LVS is a check performed between the schematic (netlist generated after synthesis at the end of LD phase) with layout(generated after PnR )

Apart from these Electrical Rule Check ERC is also performed on your design.

DRC,LVS and ERC will comprise the physical verification step of ASIC design flow.

Helpful??