melectronic
Newbie level 1
My comparator is intended to be used in a single-slope ADC,which resolution is 10 bit.
Maybe some offset cancellation tcheniques need to be used in my design.
The propogation delay of the comparator is less than 20ns.
The input range is about from 1V to 2V,and minimum resolution shoulde be below 500uV. The supply voltage of the circuit is 3.3V,implemented in 0.35um CMOS process.
Coulde you give me any advice or references on my design? How about the architechture in razavi's paper "Design techniques for high speed, high resolution comparators"?
THANKS A LOT!!
the picture below is the enviroment where the comparator works in
why no people reply my question? is there any problem in my query?
Maybe some offset cancellation tcheniques need to be used in my design.
The propogation delay of the comparator is less than 20ns.
The input range is about from 1V to 2V,and minimum resolution shoulde be below 500uV. The supply voltage of the circuit is 3.3V,implemented in 0.35um CMOS process.
Coulde you give me any advice or references on my design? How about the architechture in razavi's paper "Design techniques for high speed, high resolution comparators"?
THANKS A LOT!!
the picture below is the enviroment where the comparator works in
why no people reply my question? is there any problem in my query?