well antena errors in analog layout

[holla1112]

I am not Understaing wht s well Antena error .. can any one plz explain..
antena error will occor oly btw two area one is gate and other s connected matirial to dat.. (met1 met2 etc)
how well s connected to gate and dat may reson to distroy gate..??

 

[erikl]

Well, antenna errors are not allowed in analog layout ;-)

Antenna errors create problems only during fabrication of the wafer (at plasma etch and CMP process steps). In this phase, well and substrate are equivalent regarding charge drain-off.

 

[holla1112]

y well antena is nt in analog layout..??
well and substrate are equivalent regarding charge drain off .... wht u mean by dis..??\

can u more abt dis..??

 

[erikl]

well and substrate are equivalent regarding charge drain off .... wht u mean by dis..??\

During wafer fabrication there's no (external) voltage between well & substrate - they're just differently doped regions in the same silicon substrate, representing a floating diode. It doesn't matter where charges from antennas are drained-off to.

 

[holla1112]

During wafer fabrication there's no (external) voltage between well & substrate - they're just differently doped regions in the same silicon substrate, representing a floating diode. It doesn't matter where charges from antennas are drained-off to.

SO then there is no well antena error, not only in anlog layout in every fabrication(because every time the wafer and well creation will be same for every IC). If there is a well antena error, then where we can see that..??. If there is no such concept like well antena error why we discuess about that..??

 

[erikl]

... If there is a well antena error, then where we can see that..??

I've never seen a well antenna error mentioned - apart from you.

If there is no such concept like well antena error why we discuess about that..??

Because you started the thread on it. Actually we didn't discuss it; I just tried to convince you that it doesn't make sense, IMHO.

The only thing which makes sense in this context is a well antenna diode, which e.g. is a p⁺n diode in the n-well to drain-off antenna charges from the gate of an adjacent PMOS.