Dec 26, 2007 #1 siva_7517 Full Member level 2 Joined Jan 16, 2006 Messages 138 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,296 Activity points 2,401 Hi, Wat does this verilog operator means (!==): example A !== B
Dec 26, 2007 #2 N no_mad Full Member level 5 Joined Dec 10, 2004 Messages 271 Helped 30 Reputation 60 Reaction score 11 Trophy points 1,298 Location Naboo Activity points 2,489 verilog question Hi, It is A not equal to B, including x and z (Case inequality). Bits with x and z are included in the comparison and must match for the result to be true.
verilog question Hi, It is A not equal to B, including x and z (Case inequality). Bits with x and z are included in the comparison and must match for the result to be true.
Dec 26, 2007 #3 salma ali bakr Advanced Member level 3 Joined Jan 27, 2006 Messages 969 Helped 104 Reputation 206 Reaction score 21 Trophy points 1,298 Activity points 7,491 Re: verilog question yes !== is for inequality comparing logical values of: 0, 1, X and Z it's one of the "identity operators" while the != is for inequality comparing logical values of: 0 and 1 only it's one of the "equality operators"
Re: verilog question yes !== is for inequality comparing logical values of: 0, 1, X and Z it's one of the "identity operators" while the != is for inequality comparing logical values of: 0 and 1 only it's one of the "equality operators"
Dec 28, 2007 #4 P phoenixfeng Full Member level 2 Joined Mar 27, 2004 Messages 147 Helped 15 Reputation 30 Reaction score 6 Trophy points 1,298 Activity points 770 verilog question additionally, !== can't be synthesised but != is ok
Dec 28, 2007 #5 S syncom Junior Member level 3 Joined Sep 10, 2002 Messages 25 Helped 2 Reputation 4 Reaction score 1 Trophy points 1,283 Activity points 139 verilog question suggest to use casex , it is synthesisable..