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warnings when synthesizing design

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K

kcinimod

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Hi, can someone explain to me what the warnings mean for the below code ?
Thanks.

Code: 
library ieee;
use ieee.std_logic_1164.all;
	

entity counter is
	port( 
		clk : in std_logic;
		data : in std_logic;
		enable : in std_logic;
		compare_reset : in std_logic;
	    dout : out std_logic 
		
	);
end counter;

architecture count of counter is

signal data_sync : std_logic_vector(1 downto 0);
signal pre_count : integer;
signal pre_count_1 : integer;
signal pre_count_2 : integer;
signal data_count : integer;
signal dout_count : std_logic;




begin
	process(clk)
	begin
		if rising_edge(clk) then
			data_sync <= data_sync(0) & data;
		elsif falling_edge(clk) then
			data_sync(1) <= '0';
			
		end if;
	end process;


	count_proc : process(clk, enable, data_sync)
	begin
		if (enable = '0') then
			data_count <= 0;
			pre_count <= 0;
			pre_count_1 <= 0;
			pre_count_2 <= 0;
		
		elsif (data_sync(1) = '1') then
			
			pre_count <= 0;
		elsif rising_edge(clk) then
			pre_count <= pre_count + 1;
		end if;
		
		
				
		if (data_sync(1) = '1') then 
			if (data_count = 0) then
				pre_count <= 0;
				data_count <= data_count + 1;
			elsif (data_count = 1) then
				pre_count_1 <= pre_count;
				data_count <= data_count + 1;
			elsif (data_count = 2) then
				pre_count_2 <= pre_count;
				data_count <= data_count - 1;
			end if;
		end if;
	end process;
	
	

	compare_proc : process(pre_count_1, pre_count_2, compare_reset)
	begin
		if (compare_reset = '0') then
			dout_count <= '0';
		elsif (pre_count_2 /= 0 and dout_count = '0') then
			if (pre_count_1 > pre_count_2) then
				dout <= '1';
				dout_count <= '1';
			elsif (pre_count_1 < pre_count_2) then
				dout <= '0';
				dout_count <= '1';				
			end if;
		elsif (dout_count = '1') then 
			dout_count <= '0';
		end if;
	end process;
end count;

Code: 
@W: CL117 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":75:2:75:3|Latch generated from process for signal dout; possible missing assignment in an if or case statement.
@W: CL117 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":75:2:75:3|Latch generated from process for signal dout_count; possible missing assignment in an if or case statement.
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[0]
@W: CL180 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":61:10:61:23|Found combinational loop at un23_data_sync
@W: CL181 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[1]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[2]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[3]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[4]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[5]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[6]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[7]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[8]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[9]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[10]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[11]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[12]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[13]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[14]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[15]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[16]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[17]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[18]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[19]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[20]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[21]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[22]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[23]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[24]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[25]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[26]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[27]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[28]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[29]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[30]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop at data_count[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[30]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[29]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[28]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[27]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[26]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[25]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[24]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[23]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[22]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[21]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[20]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[19]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[18]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[17]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[16]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[15]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[14]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[13]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[12]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[11]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[10]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[9]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[8]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[7]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[6]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[5]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[4]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[3]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[2]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[1]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_1[0]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[31]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[30]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[29]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[28]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[27]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[26]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[25]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[24]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[23]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[22]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[21]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[20]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[19]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[18]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[17]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[16]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[15]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[14]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[13]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[12]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[11]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[10]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[9]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[8]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[7]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[6]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[5]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[4]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[3]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[2]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[1]
@W: CL179 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop at pre_count_2[0]
@W: CL154 :"C:\Users\HQiEn\Desktop\Dominick\vhdl tutorial\shiftregister.vhd":31:2:31:3|Clock on register data_sync tied to a constant
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count_0_sqmuxa
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net un1_pre_count9
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":58:7:58:20|Found combinational loop during mapping at net count_proc\.un21_data_sync
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_1_1[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":42:2:42:3|Found combinational loop during mapping at net count_proc\.pre_count_2_1[31]
@W: MT462 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":75:2:75:3|Net un1_dout_count8_1 appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":75:2:75:3|Net un1_dout_count9 appears to be an unidentified clock source. Assuming default frequency. 
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":22:7:22:16|Found combinational loop during mapping at net un1_data_count_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count_0_sqmuxa
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net N_135
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":58:7:58:20|Found combinational loop during mapping at net count_proc\.un21_data_sync
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net data_count[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[31]
@W: MT462 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":75:2:75:3|Net un1_dout_count8_1 appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":75:2:75:3|Net un1_dout_count9 appears to be an unidentified clock source. Assuming default frequency. 
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[1]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[0]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[3]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[2]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[5]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[4]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[7]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[6]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[9]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[8]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[11]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[10]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[13]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[12]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[15]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[14]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[18]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[19]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[16]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[17]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[22]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[23]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[20]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[21]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[26]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[27]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[24]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[25]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[30]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[31]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[28]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_2[29]
@W: BN137 :"c:\users\hqien\desktop\dominick\vhdl tutorial\shiftregister.vhd":57:2:57:3|Found combinational loop during mapping at net pre_count_1[29]
@W: MT420 |Found inferred clock counter|clk with period 1000.00ns. Please declare a user-defined clock on object "p:clk"
 

There are a number of problems with your code. Don't use both the rising and falling edge of a clock in the FPGA fabric, as FPGAs only have dual-edge flip flops on IO pads. Doing it in the fabric will make it harder to achieve timing, and there is almost never a good reason to do it.

Your second process has two asynchronous resets, which I'm not sure can be synthesised reliably (due to combinatorial LUT glitches). Reconsider your need for asynchronous reset logic.

In your final combinatorial process, you don't assign doug in every branch, so it will lead to a latch. You're also checking and assigning dout_count in a combinatorial process (if dout_count = '1' then dout_count <= '0') which doesn't make sense - without a clock and a flip-flop, this is like connecting an inverter's input to its output.

Similarly in the second process, you're assigning pre_count and data_count combinatorially, since this branch isn't covered by the if(rising_edge). Also, you are assigning values to pre_count in multiple places (after the rising_edge(clk) and in the if(data_sync(1)) branch.
 

for the first problem you highlighted, i would like to data_sync to go to '0' when clk goes to '0' (meaning to have the same pulse width), without using falling_edge, how should i go about with it ?
 

Why do you need data_sync to have the same pulse width as clk? If everything else using data_sync is synchronous to the clock, it doesn't matter what it looks like when the clock is low.

Perhaps if you can describe exactly what you are trying to achieve (do you have a timing diagram?), we can figure out how you would achieve the desired result using synthesisable VHDL.
 

i realised that i may not need that to happen, regarding the combinational loop warning, it can be solved by adding the clk signal ?
 

you need to make everything synchrnous the the clock. If you look at your current code, what you are asking the data_count signal to do is +1 in an infinitely short amount of time, followed by the next iteration and so on, in an infinite loop. Thats where the warning comes from. You cannot have a counter with some form of trigger (usually the clock).

I suggest you look at the coding guidelines for your particular tool.
 

kcinimod said:
for the first problem you highlighted, i would like to data_sync to go to '0' when clk goes to '0' (meaning to have the same pulse width), without using falling_edge, how should i go about with it ?
Click to expand...

How should you go about it? By not doing it. Rewire your brain such that this particular desire is eradicated and your problems shall be solved. ;-)

Seriously though, what you are describing is a latch. And in fpga's you just don't want that, because timing analysis is going to be crap. You are much better of sticking to the boring old plan of just the posedge or just the negedge. And not in the least because all the tools primarily have this sort of logic as focus. So this will give you the best synthesized results.

While you might think that doing things both on the posedge and on the negedge is all clever and stuff, but reality will conspire to actually make your design slower that way. Just make your design synchronous to the clock in your design as suggested, and things are suddenly a whole lot easier.
 

If you need to use both edges of the clock, just mutliply the source clock by 2, and always use the rising edge. (that gets you both edges of the slower clock.)
 
TrickyDicky said:
If you need to use both edges of the clock, just mutliply the source clock by 2, and always use the rising edge. (that gets you both edges of the slower clock.)
Click to expand...

Good point. That indeed makes things a whole lot simpler.
 

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