Warnings when synthesis using RTL compiler

[Greatrebel]

Hi All,

When I use RTL compiler to synthesis my design, I found there were a lot of warnings like

"The following sequential clock pins have no clock waveform driving them" and

"Referenced signal not in sensitivity list. This may cause simulation mismatches between the original and synthesized designs." during elaboration.

I am wondering whether these warnings are serious, can I ignore them.

Thanks in advance

 

[rca]

for the warning "Reference signal...", you should fix it and restart all your RTL simulation, because, as mentionne, the simulator can be false.

for the warning "The folowing...", you need to analyze which pins are not cover by the "create_clock", and if this acceptable, or need to be completed. In this case, this element will not correctly balance in the clock tree and could made any issue.

 

[Greatrebel]

Hi rca,

Thanks a lot!

 

[yonehara]

How can i fix the "create_clock" problem??