lanfeust129
Newbie level 2
Hello,
I've got a problem with my VHDL code. The warnings are :
WARNING:Xst:2677 - Node <half_sync_entries_2> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <half_sync_entries_3> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <half_sync_entries_4> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <half_sync_entries_5> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_2> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_3> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_4> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_5> of sequential type is unconnected in block <synchronisation_top>.
That's the code in top.vhd
And in synchronisation.vhd
I know it's a bit messy (and I don't really need half_sync_entries for example) I just want to know why it say that it's not connected...
Thanks
I've got a problem with my VHDL code. The warnings are :
WARNING:Xst:2677 - Node <half_sync_entries_2> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <half_sync_entries_3> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <half_sync_entries_4> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <half_sync_entries_5> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_2> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_3> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_4> of sequential type is unconnected in block <synchronisation_top>.
WARNING:Xst:2677 - Node <sync_entries_5> of sequential type is unconnected in block <synchronisation_top>.
That's the code in top.vhd
Code:
component synchronisation
Port ( D : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
A : in STD_LOGIC;
S : in STD_LOGIC;
P : in STD_LOGIC;
test : in STD_LOGIC;
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
sync_test : out STD_LOGIC;
sync_entries : out STD_LOGIC_VECTOR (5 downto 0));
end component;
[...]
synchronisation_top : synchronisation
port map ( D => D,
I1 => I1,
I2 => I2,
A => A,
S => S,
P => P,
test => test,
reset_n => reset_n,
clk => clk,
sync_entries => sync_entries,
sync_test => sync_test
);
And in synchronisation.vhd
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity synchronisation is
Port ( D : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
A : in STD_LOGIC;
S : in STD_LOGIC;
P : in STD_LOGIC;
test : in STD_LOGIC;
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
sync_test : out STD_LOGIC;
sync_entries : out STD_LOGIC_VECTOR (5 downto 0));
end synchronisation;
architecture Behavioral of synchronisation is
SIGNAL half_sync_entries : STD_LOGIC_VECTOR (5 downto 0);
SIGNAL half_sync_test : STD_LOGIC;
begin
HALF_SYNC: PROCESS(clk,reset_n)
BEGIN
IF reset_n = '0' THEN --reset asynchrone actif bas
half_sync_entries <= (OTHERS => '0');
half_sync_test <= '0';
ELSIF clk'EVENT AND clk = '1' THEN --flanc montant du signal clk
half_sync_entries <= D & I1 & I2 & A & S & P;
half_sync_test <= test;
END IF;
END PROCESS;
SYNC: PROCESS(clk,reset_n)
BEGIN
IF reset_n = '0' THEN --reset asynchrone actif bas
sync_entries <= (OTHERS => '0');
sync_test <= '0';
ELSIF clk'EVENT AND clk = '1' THEN --flanc montant du signal clk
sync_entries <= half_sync_entries;
sync_test <= half_sync_test;
END IF;
END PROCESS;
end Behavioral;
I know it's a bit messy (and I don't really need half_sync_entries for example) I just want to know why it say that it's not connected...
Thanks