WARNING:Xst:1290 - Hierarchical block<>is unconnected in bloc

[electronical]

Hello,I have a problem,when I synt it with ISE I face with these warning:

WARNING:Xst:1290 - Hierarchical block <Com_02> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_a> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_index_1> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_index_all> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_a0> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_a1> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_a2> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_12> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_11> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_10> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_index_0> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_index_a20> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_min_s_0> is unconnected in block <tota>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_min_s_1> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Com_01> is unconnected in block <total>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <MUX_index_a10> is unconnected in block <total>.

when I searched in internet the same warning is occured when dont use them in port as output or never used them,but I used them why these warning are occured?

code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.new_min_values_package.all;
entity CNP_VNP is
 port( abs_Mes_v_to_c:in matrix1x7positive;
out_min_1_new,out_min_2_new:out integer range 0 to 127;index_min_new:out bit_vector(2 downto 0);
    sign_value_new:out matrix1x7sign;sign_each_row_new:out integer range -1 to 1;
    L_matrix_new:inout integer range -127 to 127;add_01:inout integer range 1 to 2304
    ); 
end;
 architecture behave of CNP_VNP is
  type matrix1x4positive is array (1 to 4) of integer range 0 to 127;
 type matrix1x2positive is array (1 to 2) of integer range 0 to 127;
 component MUX_7x1 
  port(sel:in bit_vector(2 downto 0);in1:in matrix1x7positive;out1:out integer range 0 to 127);
end component;
component MUX_4x1 
  port(sel:in bit_vector(1 downto 0);in1:in bit_vector(1 to 4);out1:out bit);
end component;
component MUX_2x1 
  port(sel:in bit;in1:in bit_vector(1 to 2);out1:out bit);
end component;
component find_min_2_value 
  port(in1,in2:in integer range 0 to 127;out1:out integer range 0 to 127;ca:out bit);
end component;
component find_min_s 
  port(in1,in2:in integer range 0 to 127;out1:out integer range 0 to 127);
end component;  
signal index:integer range 1 to 7;
signal flag1:bit_vector(1 to 4);
signal flag2:bit_vector (1 to 2);
signal index_0,index_1,index_2:bit;
signal out1:matrix1x4positive;
signal out2:matrix1x2positive;
signal out_s:integer range 0 to 127;
signal sel_0,sel_4,sel_6:bit_vector(1 downto 0);
signal sel_2,sel_5,sel_7:bit_vector(2 downto 0);
signal a0,a1,a2:integer range 0 to 127;
signal sel_3,index_a10,index_a11,index_a20:bit;
signal Mes_c_to_v:integer range -127 to 127:=0;
signal out_1,out_a:integer range 0 to 127:=0;
signal c,d:integer range -254 to 127:=1; 
  begin
   Com_10:find_min_2_value port map(abs_Mes_v_to_c(1),abs_Mes_v_to_c(2),out1(1),flag1(1));
    Com_11:find_min_2_value port map(abs_Mes_v_to_c(3),abs_Mes_v_to_c(4),out1(2),flag1(2));
    Com_12:find_min_2_value port map(abs_Mes_v_to_c(5),abs_Mes_v_to_c(6),out1(3),flag1(3));
    out1(4)<=abs_Mes_v_to_c(7) when length_row=8 else max_value;
    flag1(4)<='0';
    Com_01:find_min_2_value port map(out1(1),out1(2),out2(1),flag2(1));
    Com_02:find_min_2_value port map(out1(3),out1(4),out2(2),flag2(2));
    Com_a :find_min_2_value port map(out2(1),out2(2),out_min_1_new,index_2);
    MUX_index_1 :MUX_2x1 port map(index_2,flag2,index_1);
    sel_0<=index_2 & index_1;
    MUX_index_0:MUX_4x1 port map(sel_0,flag1,index_0);
    index_min_new<=sel_0 & index_0;
    sel_2<=sel_0 & not(index_0);
    MUX_a0:MUX_7x1 port map(sel_2,abs_Mes_v_to_c,a0);
    sel_3<=not index_2;
    MUX_index_all: MUX_2x1 port map(sel_3,flag2,index_a11);
    sel_4<=not index_2 & index_a11;
    MUX_index_a10 :MUX_4x1 port map(sel_4,flag1,index_a10);
    sel_5<=not(index_2) & index_a11 & index_a10;
    MUX_a1:MUX_7x1 port map (sel_5,abs_Mes_v_to_c,a1);
    sel_6<=index_2 & not index_1;
    MUX_index_a20 :MUX_4x1 port map (sel_6,flag1,index_a20);
    sel_7<=index_2 & not index_1 & index_a20;
    MUX_a2 : MUX_7x1 port map (sel_7,abs_Mes_v_to_c,a2);
   Com_min_s_0: find_min_s port map(a0,a1,out_s);
   Com_min_s_1:find_min_s port map(out_s,a2,out_min_2_new);    
          
end;

 

[mrflibble]

Without even reading the rest ...

same warning is occured when dont use them in port as output or never used them,but I used them why these warning are occured?

"But I used them" generally means "but I think I used them, but really I didn't". Put another way, "signal not used" can be read as "output does not depend on this signal". No doubt you connected it. Who cares? The tools don't. If all the design OUTPUTS can be resolved regardless of whatever value a certain signal may be, then that signal will be optimized away (it's treated as a don't care). And when optimized away, you can get "unconnected signal" warnings.

 

[electronical]

tankyou.
ok what am i doing that these warnings dont appear?
are these warnings important?

 

[mrflibble]

Not that important. What would be more important (in terms of what to spend your time on), would be to make a testbench and check if your design works. Because chances are that 1) you get this type of warning and 2) the design still works as intended.

Essentially these warnings mean that you thought up a nice module with all sorts of signals. But in the end the module outputs do not depend on all the signals in it. In other words, the optimizer can just remove these signals and you would not know the difference. So it removes those, and the circuit will still work as with these signals present (and not doing anything).

If I make two modules, counter and consumer... counter is a 32-bit counter happily counting up. I feed this 32-bit counter result to my consumer module. The consumer module takes the 32-bit input ... and only does something with say the 4 first LSB. Why because I designed my consumer module that way for whatever reason. So ISE comes along and sees that you won't know the difference if those other 28 bits get removed. So it'll remove that, and you'll get warnings about it. But the design still works.